The phase change memory device is a storage device using a phase change layer (chalcogenide alloy and the like) having the electrical resistance varying corresponding to its crystalline state, as a memory element. The chalcogenide alloy is an amorphous semiconductor including a chalcoge element.
FIG. 21 is a view showing part of the periodic table to explain chalcoge elements.
As shown in the figure, chalcoge elements include S (sulfur), Se (selenium) and Te (tellurium) of the sixth group of the periodic table. Application fields of the chalcogenide alloy are broadly divided into the optical disk and electrical memory. As a chalcogenide alloy used in the field of the electrical memory, there are known GeSbTe (hereinafter, referred to as GST) that is a compound of Ge (germanium), Te (tellurium) and Sb (antimony), AsSbTe, SeSbTe and the like.
FIGS. 22A and 22B are views to explain the principle of the phase change memory.
As shown in FIG. 22A, the chalcogenide alloy can form two stable states, an amorphous semiconductor state 10 and crystalline state 30, and it is necessary to supply heat exceeding an energy barrier 20 to cause transition from the amorphous state 10 to crystalline state 30.
As shown in FIG. 22B, the chalcogenide alloy of the amorphous state indicates high resistance. The high resistance state corresponds to a digital value of “1”. The chalcogenide alloy of the crystalline state indicates low resistance. The low resistance state corresponds to a digital value of “0”. Thus, by detecting a difference between current amounts (or voltage drop) passed through the chalcogenide alloy, it is possible to determine whether the storage information is “1” or “0”, (i.e. to read the information).
Joule heat is used as heat to supply to the chalcogenide alloy for phase transition. In other words, by supplying pulses with different peak values and different durations to the chalcogenide alloy, Joule heat is generated in a contact face between an electrode and the chalcogenide alloy and its vicinity. The phase of the chalcogenide alloy changes by the Joule heat.
More specifically, the chalcogenide alloy becomes an amorphous state when supplied with heat near its melting point for a short time and cooled rapidly. Meanwhile, the chalcogenide alloy becomes a crystalline state when supplied with heat of its crystallization point lower than the melting point for a long time and then cooled.
For example, when GST is supplied with heat near its melting point (about 610° C.) for a short time (1 to 10 ns) and then cooled rapidly (for about 1 ns), GST becomes an amorphous state. Meanwhile, when GST is supplied with heat of its crystallization point (about 450° C.) for a long time (30 to 50 ns) and then cooled, GST becomes a crystalline state.
As shown in FIG. 22B, causing transition from the amorphous state to crystalline state is called “set (crystallization process)”, and a pulse supplied to the chalcogenide alloy is called a “set pulse”. It is herein assumed that the minimum temperature (crystallization temperature) required for crystallization is Tc, and that the minimum time (crystallization time) required for crystallization is tr.
Inversely, causing transition from the crystalline state to amorphous state is called “reset (non-crystallization process)”, and a pulse supplied to the chalcogenide alloy is called a “reset pulse”. The heat supplied to the chalcogenide alloy has temperatures near the melting point Tm, and the chalcogenide alloy is cooled rapidly after melting.
FIGS. 23A to 23D are views to explain a basic structure of a phase change memory device and the set/reset operation of the phase change memory device.
As shown in FIG. 23A, the phase change memory device basically has a structure that a chalcogenide alloy layer (phase change layer) 46 is sandwiched between upper and lower electrodes (48, 42). In addition, reference numeral 40 denotes a substrate, and reference numeral 44 denotes an electrical insulating film. A terminal P to which a set pulse or the like is applied is connected to the upper electrode 48, and the lower electrode 42 is fixed to the ground (reference potential).
As shown in FIG. 23B, the phase change memory device in FIG. 23A is equivalent to a resistance R1. As described above, a resistance value of the resistance R1 varies according to whether the chalcogenide alloy layer is an amorphous state or crystalline state. As shown at the left side in FIG. 23B, three kinds of pulses are input to the terminal P. A set pulse S1 has a peak value exceeding a threshold Vth. A reset pulse S2 has a peak value higher than that of the set pulse S1 and a width shorter than that of the set pulse S1. A read pulse S3 has a peak value less than the threshold Vth and a width wider than that of the set pulse S1. Herein, Vth is a voltage of lower limit to enable generation of Joule heat required for crystallization.
FIG. 23C shows correspondence between the set pulse S1 and increases in temperature caused by Joule heat generated by supply of the set pulse S1. FIG. 23C shows a waveform of the voltage on the upper side, and increases in temperature by Joule heat on the lower side.
A value of the voltage of the set pulse S1 exceeds the predetermined threshold Vth, and a time duration of the pulse is tcry. tcry is longer than the crystallization time tr (minimum time required for crystallization of the chalcogenide alloy). The temperature increased by Joule heat is significantly lower than melting point Tm, while being higher than the minimum temperature Tc (crystallization temperature) required for crystallization.
FIG. 23D shows correspondence between the reset pulse S2 and increases in temperature caused by Joule heat generated by supply of the reset pulse S2. FIG. 23D shows a waveform of the voltage on the upper side, and increases in temperature by Joule heat on the lower side.
As shown in the figure, a peak value of the reset pulse S2 largely exceeds the threshold Vth for crystallization, and a width of the pulse is sufficiently narrow. The increased temperature by Joule heat thereby exceeds melting point Tm of the chalcogenide alloy. Further, the time tamo taken from the peak of the increased temperature to crystallization temperature Tc is adequately short. The chalcogenide alloy is thereby once melted and then cooled rapidly, and as a result, is reset to an amorphous state.
FIG. 24 is a circuit diagram to explain the read operation in the phase change memory device. In FIG. 24, common portions to those in the figures described above are assigned the same reference numerals.
In FIG. 24, W indicates a word line, G indicates a ground line, and B indicates a bit line (that is a pulse input line connected to the terminal P to input the set pulse S1, reset pulse S2 and read pulse S3). Further, R1 indicates an equivalent resistance of the phase change memory element (comprised of a chalcogenide alloy layer 60).
M4 indicates an NMOS transistor (switching element) to select a memory cell, R2 indicates a current/voltage conversion resistance, A1 indicates a sense amplifier, and reference numeral 62 denotes a reference voltage source of the sense amplifier A1. I1 indicates a current passed through the memory cell in the read operation, and Vout indicates an output voltage (sensing output) of the sense amplifier A1.
In the set operation (in the same way as in the reset operation and read operation), the NMOS transistor M4 is turned on with the word line W being an active line, and then, a required pulse (one of S1 to S3) is input from the terminal P. The read pulse S3 is input in the read operation.
A resistance value of the resistance R1 varies whether the chalcogenide alloy layer 60 constituting a memory cell is an amorphous state or crystalline state, and in response to the resistance value, a current amount of the current I1 varies. Accordingly, by converting the current amount into a voltage value to read, it is possible to determine whether the stored information is “1” or “0”.
The inventor of the present invention made various studies on the structure of the phase change memory device before the invention, and as a result of the study, found that following inconveniences can occur in the conventional structure.
As shown in FIG. 23A, the phase change memory device generally adopts a basic structure where a phase change layer (for example, GST) is sandwiched between upper and lower electrodes (for example, see JP 2005-159325). In other words, an electrode made of metal such as tungsten or the like exists on the phase change layer. The upper electrode made of metal such as tungsten or the like also has heat radiation characteristics. Accordingly, the conventional phase change memory element is regarded as having a structure such that a radiating fin is formed immediately above the phase change area.
As described above, since phase transition of the chalcogenide alloy layer is implemented by using Joule heat caused by applying the current, dissipation of Joule heat via the upper electrode (upper metal layer) leads to a reduction in thermal efficiency and is not preferable.
The reduction in thermal efficiency does not become a significant problem at the prototyping stage of discrete phase change memory element and memory LSI with a low degree of integration, but becomes a serious problem at the actual mass production stage of phase change memory device with a high degree of integration using the fine patterning process.
In other words, to increase the capacity of a phase change memory device, it is required to decrease the size of the memory cell, and therefore, a reduction in reset current (that is to restore the phase change layer from the crystalline state to amorphous state) is an important issue. That is, when a metal layer is laminated on the phase change layer, the upper metal layer functions as a radiating fin, and the thermal efficiency deteriorates, resulting in a factor for prohibiting the reduction in the current amount of the reset current. It is thus not possible to achieve a large scale of phase change memory LSI.
A technique is disclosed in JP 2003-332529 where a lower electrode (heater electrode) is formed in a shape with a pointed top, the contact face between the electrode and the phase change layer is thereby minimized to decrease the current, and radiation is thus suppressed. However, to process the lower electrode to the shape with a pointed top, specialized manufacturing process technique is required that is not used in typical LSI manufacturing, and it is undeniable that such a technique results in increases in complexity and cost.
Further, the upper metal layer has a predetermined thickness, and therefore, the heat also escapes from the side portion of the upper metal. Accordingly, decreasing the thickness of the upper metal layer is considered to suppress heat dissipation from the upper metal layer as much as possible. However, the decrease in the thickness of the upper metal layer makes the cross-sectional area smaller, increases the wiring resistance, and results in deterioration in circuit characteristics.
The upper metal layer acts as an etching stopper in making an opening for a contact hole in an interlayer insulating film, and prevents the undercoated phase change layer (for example, GST film) from being exposed. Accordingly, when the upper metal layer is thinned, in forming contact holes in the interlayer insulating film by etching, a risk occurs that the upper metal layer is penetrated, the phase change layer (for example, GST film) is exposed, and components of the phase change layer are volatilized and pollute the line.
When the phase change layer is partially exposed, such a problem may arise that components of the phase change layer are sublimated and disappear by heat treatment subsequently performed in embedding a metal layer to be contact electrodes. Further, it is feared that component gases of the phase change layer fill the contact hole, an adequate amount of the metal gas to form the contact electrode cannot reach the inside of the contact hole, and that failure occurs in growth of the embedded electrode.
Further, as described previously, the adhesion between the phase change layer and interlayer insulating film is regarded as being not good, and an adhesion layer comprised of an extremely thin film of metal such as titanium (Ti) or the like is sometimes provided between the layer and film. In this case, since the adhesion layer (Ti or the like) contacts the bottom of the phase change layer (for example, GST film), it may occur that components of both layers are bonded (for example, Ti (titanium) and Te (tellurium) are bonded), and the composition of the phase change layer changes in the contact face between the phase change layer and adhesion layer and its vicinity, resulting in an adverse effect on rewritable characteristics of the phase change layer.
Furthermore, the upper metal layer needs to be always provided to cover the top face of the phase change layer (GST film). In other words, the upper metal layer and the phase change layer (GST film) are paired, and cannot be divided in integration. Accordingly, it is not possible to use the upper metal layer in forming wiring and electrode in a peripheral circuit. Therefore, in forming wiring and electrode in a peripheral circuit, independently of processes of forming and processing a metal layer in a memory cell portion, it is necessary to newly add processes of forming and processing a metal layer, and the manufacturing process cannot be simplified.
Thus, it is undeniable that the thermal efficiency in writing (particularly, in reset) deteriorates in the phase change memory device with the conventional structure. Further, as described above, the problems exist in the mass production of a large scale of phase change memory LSI.
The present invention has been carried out based on the aforementioned consideration, and it is an object of the invention to achieve a phase change memory device of a structure with high thermal efficiency, and enable mass production of a large scale of phase change memory LSI while solving the problems due to mass production of the phase change memory device.